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BSI
FEATURES
Low Power/Voltage CMOS SRAM 512K X 8 bit
GENERAL DESCRIPTION
BS62LV4005
* Vcc operation voltage : 4.5V ~ 5.5V * Low power consumption Vcc = 5.0V C-grade: 45mA (Max.) operating current I -grade: 50mA (Max.) operating current 1.5uA (Typ.) CMOS standby current * High speed access time : -70 70ns (Max.) at Vcc = 5.0V -55 55ns (Max.) at Vcc = 5.0V * Automatic power down when chip is deselected * Three state outputs and TTL compatible * Fully static operation * Data retention supply voltage as low as 1.5V * Easy expansion with CE and OE options
The BS62LV4005 is a high performance, low power CMOS Static Random Access Memory organized as 524,288 words by 8 bits and operates from a wide range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with maximum access time of 55/ 70ns in 5V operation. Easy memory expansion is provided by active LOW chip enable (CE), active LOW output enable (OE) and three-state output drivers. The BS62LV4005 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV4005 is available in the JEDEC standard 32 pin SOP , TSOP, TSOP II and STSOP .
PRODUCT FAMILY
PRODUCT FAMILY BS62LV4005SC BS62LV4005EC BS62LV4005TC BS62LV4005STC BS62LV4005PC BS62LV4005SI BS62LV4005EI BS62LV4005TI BS62LV4005STI BS62LV4005PI OPERATING TEMPERATURE Vcc RANGE SPEED ( ns ) Vcc = 5.0V
( ICCSB1 , Max )
POWER DISSIPATION STANDBY Operating
( ICC, Max )
PKG TYPE SOP-32 TSOP2-32 TSOP-32 STSOP-32 PDIP-32 SOP-32 TSOP2-32 TSOP-32 STSOP-32 PDIP-32
Vcc = 5.0V
Vcc=5.0V
+0 O C to +70O C
4.5V ~ 5.5V
55 / 70
15uA
45mA
-40 O C to +85O C
4.5V ~ 5.5V
55 / 70
25uA
50mA
PIN CONFIGURATIONS
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 BS62LV4005SC 9 BS62LV4005SI 10 BS62LV4005EC BS62LV4005EI 11 BS62LV4005PC 12 BS62LV4005PI 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
FUNCTIONAL BLOCK DIAGRAM
*
A13 A17 A15 A18 A16 A14 A12 A7 A6 A5 A4
Address Input Buffer
22
Row Decoder
2048
Memory Array 2048 X 2048
2048 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 8 Data Input Buffer 8 Column I/O Write Driver Sense Amp 256 Column Decoder 16 CE WE OE Vdd Gnd A11 A9 A8 A3 A2 A1 A0 A10 Control Address Input Buffer
8
A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
BS62LV4005TC BS62LV4005STC BS62LV4005TI BS62LV4005STI
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3
Data Output Buffer
8
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62LV4005
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Revision 2.4 April 2002
BSI
PIN DESCRIPTIONS
BS62LV4005
Function
These 19 address inputs select one of the 524,288 x 8-bit words in the RAM CE is active LOW. Chip enable must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected.
Name
A0-A18 Address Input CE Chip Enable Input
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0-DQ7 Data Input/Output Ports Vcc Gnd
These 8 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground
TRUTH TABLE
MODE Not selected Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O OPERATION High Z High Z DOUT DIN Vcc CURRENT ICCSB, ICCSB1 ICC ICC ICC
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL V TERM T BIAS T STG PT I OUT PARAMETER
Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to 6.0 -40 to +125 -60 to +150 1.0 20
RANGE
Commercial Industrial
AMBIENT TEMPERATURE
0 O C to +70 O C -40 O C to +85 O C
Vcc
4.5~5.5V 4.5~5.5V
C C
O
W mA
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CIN CDQ
VIN=0V VI/O=0V
6 8
pF pF
1. This parameter is guaranteed and not tested.
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BSI
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
PARAMETER NAME
VIL VIH IIL IOL VOL VOH ICC
BS62LV4005
TEST CONDITIONS
Vcc=5.0V Vcc=5.0V
PARAMETER
Guaranteed Input Low (2) Voltage Guaranteed Input High Voltage(2) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL
MIN. TYP. (1) MAX.
-0.5 2.2 --Vcc=5.0V Vcc=5.0V Vcc=5.0V
UNITS V V uA uA V V mA
--------
0.8 Vcc+0.3 1 1 0.4 -45
Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE = VIH, or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL = 2mA Vcc = Min, IOH = -1mA CE = VIL, IDQ = 0mA, F = Fmax(3)
-2.4 --
ICCSB
CE = VIH, IDQ = 0mA CE VIN Vcc-0.2V, Vcc - 0.2V or VIN
Vcc=5.0V
--
--
2
mA
ICCSB1
Standby Current-CMOS
0.2V
Vcc=5.0V
--
1.5
15
uA
1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC .
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL
VDR ICCDR tCDR tR
PARAMETER
Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time CE VIN CE VIN
TEST CONDITIONS
Vcc - 0.2V Vcc - 0.2V or VIN Vcc - 0.2V Vcc - 0.2V or VIN 0.2V 0.2V
MIN.
1.5 -0
TYP. (1)
-0.1 ---
MAX.
-1.5 ---
UNITS
V uA ns ns
See Retention Waveform
TRC (2)
1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM
( CE Controlled )
Data Retention Mode
Vcc
VIH
Vcc
VDR 2.0V
Vcc
t CDR
CE Vcc - 0.2V
tR
VIH
CE
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BSI
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0 5ns 0.5Vcc
WAVEFORM INPUTS
BS62LV4005
KEY TO SWITCHING WAVEFORMS
OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE "OFF "STATE
MUST BE STEADY MAY CHANGE FROM H TO L
1928
AC TEST LOADS AND WAVEFORMS
5.0V OUTPUT
100PF
INCLUDING JIG AND SCOPE
1928
5.0V OUTPUT
MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY
,
5PF 1020
INCLUDING JIG AND SCOPE
1020
FIGURE 1A
THEVENIN EQUIVALENT 667 ALL INPUT PULSES
FIGURE 1B
OUTPUT
1.73V
Vcc GND
10%
90% 90%
10%
5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V )
READ CYCLE JEDEC PARAMETER PARAMETER NAME NAME DESCRIPTION
Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Output Disable to Output in High Z Output Disable to Output Address Change
BS62LV4005-55 MIN. TYP. MAX.
55 ---10 10 0 0 10 ----------55 55 30 --30 25 --
BS62LV4005 -70 MIN. TYP. MAX.
70 ---10 10 0 0 10 ----------70 70 35 --35 30 --
UNIT
ns ns ns ns ns ns ns ns ns
t AVAX t AVQV t ELQV t GLQV t ELQX t GLQX t EHQZ t GHQZ t AXOX
t RC t AA t ACS t OE t CLZ t OLZ t CHZ t OHZ t OH
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SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4)
BS62LV4005
t RC
ADDRESS
t
D OUT
t
OH
AA
t OH
READ CYCLE2 (1,3,4)
CE
t t
D OUT
(5) CLZ
ACS
t CHZ
(5)
READ CYCLE3 (1,4)
t RC
ADDRESS
t
OE
AA
t
CE
t OH
OE
t t ACS t
(5) CLZ
OLZ
t OHZ (5) (1,5) t CHZ
D OUT
NOTES: 1. WE is high for read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL .
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested.
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AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V )
WRITE CYCLE
JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Write Cycle Time Chip Select to End of Write Address Set up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End ot Write to Output Active (CE , WE)
BS62LV4005 - 55 MIN. TYP. MAX.
BS62LV4005
BS62LV4005 - 70 MIN. TYP. MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns
t AVAX
t WC t CW t
AS
55 55 0 55 30 0 0 25 0 0 5
---------------25 --25 --
70 70 0 70 35 0 0 30 0 0 5
------------
------30 --30 --
tE1LWH t AVWL t AVWH t WLWH t WHAX t WLOZ t DVWH t WHDX t GHOZ t WHQX
t AW t WP t WR t WHZ t DW t DH t OHZ t OW
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t WC
ADDRESS
t WR
OE
(3)
t CW
CE
(5)
(11)
t AW
WE
t AS
(4,10)
t WP
(2)
t OHZ
D OUT
t DH t DW
D IN
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BSI
WRITE CYCLE2 (1,6)
BS62LV4005
t
WC
ADDRESS
(11) (5)
t t AW
CW
CE
t WP
(2)
WE
t AS
(4,10)
t
DH
t WHZ
D OUT
(7)
(8)
t DW t DH
(8,9)
D IN
NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write.
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Revision 2.4 April 2002
BSI
ORDERING INFORMATION
BS62LV4005
BS62LV4005
XX
YY
SPEED 70: 70ns 55: 55ns GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE S: SOP E: TSOP 2 T: TSOP ST: Small TSOP P: PDIP
PACKAGE DIMENSIONS
WITH PLATING
b
c c1
BASE METAL
b1
SECTION A-A
SOP -32
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Revision 2.4 April 2002
BSI
PACKAGE DIMENSIONS (continued)
BS62LV4005
TSOP2 - 32
TSOP - 32
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PACKAGE DIMENSIONS (continued)
BS62LV4005
STSOP - 32
PDIP - 32
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Revision 2.4 April 2002
BSI
REVISION HISTORY
Revision
2.2 2.3 2.4
BS62LV4005
Description
2001 Data Sheet release
Date
Apr. 15, 2001
Note
Modify Standby Current (Typ. and Jun. 29, 2001 Max.) Modify some AC parameters. April,10,2002
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Revision 2.4 April 2002

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